
S T 3 4 5 2 0 A   M E D A L I S T P R O    SEAGATE
                                                      Native|  Translation
                                                      ------+-----+-----+-----
Form                 3.5"/SLIMLINE         Cylinders        | 9408|  588| 1024
Capacity form/unform  4551/      MB        Heads           4|   15|     |   16
Seek time   / track  10.0/ 3.0 ms          Sector/track     |   63|   63|   63
Controller           IDE / ATA4 ULTRA      Precompensation
Cache/Buffer           512 KB              Landing Zone
Data transfer rate   24.000 MB/S int       Bytes/Sector      512
                     33.300 MB/S ext UDMA2
Recording method     EPRML16/17,ZBR                 operating  | non-operating
                                                  -------------+--------------
Supply voltage     5/12 V       Temperature *C         5 55    |    -40 70
Power: sleep              W     Humidity     %                 |
       standby        3.0 W     Altitude    km                 |
       idle          11.0 W     Shock        g        10       |    100
       seek          13.0 W     Rotation   RPM      7200
       read/write         W     Acoustic   dBA        29
       spin-up            W     ECC        Bit   SMART
                                MTBF         h     400000
                                Warranty Month        36
Lift/Lock/Park     YES          Certificates


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                      J   U   M   P   E   R   S
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SEAGATE  ST34520A  JUMPER SETTING

 Jumper Setting
 ==============

              J2  40 pin   I/O Cable Connection
                 |
                 |             J5
      +---------- ---------+G------A-+---------+    TOP (HDA)
  ----+::::::::::*::::::::1| :-: :-: | X X X X +---
      +----------+---------+H+-+-+-+-+-5-G-G-12+    BOTTOM
                 |           | | | |
 pin-20 removed -+           | | | +- Alternate Capacity (see below)
                             | | |    (spare jumpers stored on pins
                             | | |    (A-C and pins E-G)
                             | | +---- Remote LED (C-, D+)
                             | +------ Cable Select (when Slave OFF)
                             +-------- Master ON, Slave OFF

 Alternate Capacity jumper sets the default cylinder translation
 to 4092 to solve issues with certain BIOS that only auto-detect.
 Total available sectors are still at full capacity as reported via
 Identify Drive data words 52-61. Third party partitioning software
 may be needed to achieve full capacity if this option jumper is used.



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                      G   E   N   E   R   A   L
**********************************************************************
SEAGATE   ATA-INTERFACE

 ATA Interface Reference Manual 36111-001, Rev. C 21 May 1993
 1993 Seagate Technology, Inc. All rights reserved
 Publication Number: 36111-001, Rev. C

 Introduction
 ------------
 This manual describes Seagate Technology s implementation of the AT
 Attachment (ATA) interface, an intelligent hard disc drive interface
 for use in personal computer systems. This manual includes supported
 ATA interface commands, command execution, translation methodology,
 caching, power management, signal conventions, line specifications,
 and interpretations of error conditions. These interface descriptions
 are based on the draft proposed American National Standard (dpANS)
 ATA Interface Revision 4.0. For information on a particular Seagate
 ATA interface drive (including any drive-unique features not listed
 in this document), refer to the product manual for the specific
 drive.


 Advantages of the ATA interface
 -------------------------------
 The ATA interface is a natural extension of the ISA system bus. Most
 of the signals and circuitry necessary for the interface are already
 present in the host system. The interface is easily implemented into
 the design of an ISA or EISA system with little or no extension
 required in the system software. It is for this reason that the ATA
 interface standard has gained such wide acceptance in the personal
 computer industry. The ATA interface is designated as a logic-level
 interface, and responds to high-level commands from the host. The
 drive itself is an intelligent device with an embedded controller
 that interprets and executes the commands sent from the host. After
 command execution, the drive reports information on successful
 command completion, any error conditions and all parameters
 appropriate to drive status queries.


 Origins and implementation history
 ----------------------------------
 The ATA interface has evolved rapidly since its initial design by
 Compaq Corporation. After refining the basic ATA interface concepts
 and circuitry, Compaq Corporation worked with Imprimis (now a part of
 Seagate) to build the first ATA interface drive. At this stage, the
 interface was far from being an accepted standard. However, it was a
 natural extension of the ATA I/O bus, and gained industry-wide
 acceptance because most of the necessary framework needed for the
 implementation was already present in the host machine.

 Initially, there were no industry-wide standards for implementing the
 ATA interface, leaving manufacturers free to extend and improve upon
 it. In the latter part of 1988, a Common Access Method (CAM)
 committee was established to develop such standards. Their results
 were adopted by the American National Standards Institute (ANSI) with
 the intent of creating a common ATA command specification.
 The ANSI standard for the ATA interface now provides specifications
 for mandatory commands, signal conventions, register descriptions and
 other information necessary for basic compatibility across
 manufacturers and platforms. The current ANSI specification includes
 provisions for extended features such as caching and power
 management, while also providing options for vendor-specific
 enhancements.


 Nomenclature and conventions
 ----------------------------
 Throughout this manual, the term master refers to Drive 0 in a
 two-drive system; the term slave refers to Drive 1, if present.

 Signals may be asserted or negated. A signal that is asserted as a
 higher positive voltage is referred to as active high. A signal that
 is asserted as a lower (positive) voltage is referred to as active
 low, and is indicated by a minus sign (-) following the signal name.


 ATA cables and connectors
 -------------------------
 The standard ATA interface cable is a 40-conductor nonshielded cable.
 The cable should be no more than 18 inches (457 mm) long, with
 connectors that provide strain relief and are keyed at pin 20. Two
 types of connectors are used on Seagate s ATA-capable drives: a
 40-pin connector for 5.25-and 3.5-inch drives, and a 50-pin connector
 for 2.5- and 1.8-inch drives.


 Connector used on 5.25- and 3.5-inch drives
 -------------------------------------------
 The standard connector used on 5.25- and 3.5-inch drives has 40 pin
 positions in 2 rows of 20 pins each, on 100 mil (0.1 inch) centers.
 Pin 20 is removed for keying. The mating cable connector is a keyed,
 40-pin-position nonshielded female connector with 2 rows of 20
 contacts on 100 mil centers. For 5.25- and 3.5-inch drives,
 power is supplied to the drive through a separate 4-conductor cable.

 Seagate recommends using 40-pin connectors such as AMP part number
 1-499496-0, Du Pont part number 66900-040, or equivalent.


 Connector used on 2.5-inch drives
 ---------------------------------
 The ATA connector on 2.5-inch drives has 50 pin positions. In
 addition to the key pin, one pair of pins is removed, and the four
 end pins are used as jumpers for master/slave configurations.
 This leaves 44 pins to supply power and conduct signals to and from
 the drive.

 The signal pins (1 through 40) are assigned the same signals as in
 the 40-pin connector used for 5.25- and 3.5-inch drives. Power is
 supplied through pins 41, 42 and 43. The mating cable connector is a
 44-conductor nonshielded connector with 2 rows of 22 female contacts
 on 0.079-inch (2 mm) centers.

 We recommend using a connector such as Molex part number 87259-
 4413 or equivalent for 2.5-inch drives attached to flexible cables or
 printed circuit cables. Some Seagate 2.5-inch drives are designed to
 support the industry-standard MCC direct-mounting specifications (see
 drive product manual for details). MCC-compatible connectors (such as
 Molex part number 87368-442 x or equivalent) and mounting hardware
 must be used with these drives in fixed-mounting applications.


 System configurations
 ---------------------
 Seagate recommends using the ATA interface in one of the following
 configurations:

 - If the system motherboard has its own ATA connector, then you can
   connect the drive interface cable directly to the system
   motherboard.

 - If the system does not have a built-in ATA connector, then attach
   the interface cable to a Seagate ST07A or ST08A host adapter
   installed in a system expansion slot.


 Signal / Pin descriptions
 -------------------------
 Note. Not all Seagate drives support the full complement of ATA
 signals listed below. To determine the complete set of signals that
 are supported by a particular Seagate drive, see the product manual
 for that drive.

 Data lines to and from host. These comprise the 16-bit tristate,
 bidirectional data bus between host and drive. The lower 8-bits of
 host data (0 7) are used for register and ECC access. All 16 bits are
 used for data transfers.

 19 Ground Grounding pin
 20 Key An unused pin, which is clipped off at the drive to allow
    keyed cable attachment.
 21 DMARQ DMA Request (optional)
 22 Ground Grounding pin
 23 DIOW Drive I/O write strobe. Rising edge clocks data from the host
    data bus to a drive register or data port.
 24 Ground Grounding pin
 25 DIOR Drive I/O read strobe. Falling edge enables data from a drive
    register or data port to host data bus.
 26 Ground Grounding pin
 27 IORDY I/O Channel Ready (optional) - a tristate signal.
 28 SPSYNC or CSEL (optional) SPSYNC is an interdrive clock
    signal sent from the master drive to the slave drive to allow the
    slave to synchronize its spindle motor to the master drive's
    spindle motor. CSEL is used to differentiate master from slave in
    a two-drive system.
 29 DMACK DMA Acknowledge (optional)
 30 Ground Grounding pin
 31 INTRQ A tristate signal used to interrupt the host system.
    Asserted only when the drive has a pending interrupt, the drive is
    selected, and the host has cleared nIEN in the Device Control
    register.
 32 IOCS16 A tristate signal that, when active, indicates to the host
    system that the 16-bit data port has been addressed and that the
    drive is prepared to send or receive a 16-bit data word.
 33 DA1 Drive I/O address line 1: a 3-bit binary coded address
    asserted by the host to access a register or data port in the
    drive.
 34 PDIAG Passed diagnostics. Used by slave to signal to master drive
    that slave has passed its internal diagnostics.
 35 DA0 Drive I/O address line 0 (see DA1 above).
 36 DA2 Drive I/O address line 2 (see DA1 above).
 37 CS1FX Drive I/O chip select decoded from host address lines. When
    active, one of the registers in the Command Block is selected.
 38 CS3FX Drive I/O chip select decoded from host address lines. When
    active, one of the registers in the Control Block is selected.
 39 DASP Dual purpose pin:
    1) When drive is slave (SLV), this pin is used during power up to
       signal to the master that a slave is present.
    2) At all other times, the signal is active when the drive is
       executing a command, and can be used by the host I/O adapter to
       send an activity signal to an LED.
 40 Ground Grounding pin


 Interface handshaking
 ---------------------
 The main handshaking signals between the drive and the host are the
 busy bit (BSY) and the data request bit (DRQ) (in the status
 register) and the interrupt (INTRQ) signal. They can be set in one of
 the following ways:

 - Any reset will cause BSY to be set.
 - Writing a command to the command register will also set BSY.

 The BSY bit is used to indicate that the controller is busy and
 should not be accessed.

 The DRQ bit is used to control the data transfer to and from the
 controller.

 The host can read/write the data register only when the DRQ bit is
 set to 1. The INTRQ signal is generated by the drive to interrupt the
 host. For example, during a Read Sector command, the drive generates
 an INTRQ to the host whenever a sector is ready for the host to read.
 No INTRQ is generated immediately after completion of a Read command.
 The number of interrupts equals the number of sectors read.

 During a Write Sector command, the drive generates an INTRQ whenever
 the drive requests data from the host (except for the first sector).
 The drive also generates an interrupt immediately after completion of
 a Write command. The number of interrupts equals the number of
 sectors written.


 ATA interface I/O registers
 ---------------------------
 The drive communicates with the host system through an I/O register
 that routes the input and output data between registers. These
 registers are selected by codes on the CS1FX, CS3FX, DA2, DA1, DA0,
 DIOR (read) and DIOW (write) lines from the host.

 The I/O register routes data between 14 registers. Ten registers are
 used for commands to the drive or status reports from the drive, one
 register is used for data, and three registers are used for control
 and alternate status.

 These registers can be divided into two groups: Command Block
 registers and Control Block registers.

 PC-AT I/O port address: 3F6H
 This register contains the same information as the Status register in
 the command block. The only difference is that reading this register
 does not imply interrupt acknowledge or reset a pending interrupt.
 This register can be read at any time.

 PC-AT I/O port address: 1F7H
 This eight-bit register contains the host command. When this register
 is written, the drive immediately begins executing the command. The
 host must ensure that the BSY bit in the Status register is set to 0.

 All other setup registers must be written to (with appropriate
 values) before the command register can be written.

 PC-AT I/O port address: 1F5H
 This register contains the most significant bits of the starting
 cylinder address for any disc access. At the completion of a command,
 this register is updated to reflect the current cylinder address.
 With logical block addressing, this register contains bits 23 through
 16 of the LBA.

 Cylinder Low register
 PC-AT I/O port address: 1F4H
 This register contains the eight least significant bits of the
 starting cylinder address for any disc access. At the completion of a
 command, this register is updated to reflect the current cylinder
 address.

 With logical block addressing, this register contains bits 15 through
 8 of the LBA.


 Data register
 PC-AT I/O port address: 1F0H
 This is the register through which:
 - All data is passed during Read and Write commands.
 - The sector table is transferred during format commands.
 The host can only access this register when the DRQ bit in the status
 register is set to 1. All transfers use 16-bit words, except the ECC
 bytes transferred during Read Long and Write Long commands, which use
 8 bit bytes.


 Drive/Head register
 The host selects between the master and slave drives based on the DRV
 bit in the drive/head register. When the DRV bit is not set, the
 master drive is selected, and when the DRV bit is set to 1, the slave
 drive is selected. Seagate drives are designated as master and slave
 by setting the appropriate jumpers.


 Error register
 PC-AT I/O port address: 1F1H
 This register contains the status from the last command executed by
 the drive, or it may contain a diagnostic code. At the completion of
 any command except Execute Drive Diagnostic, the contents of this
 register are valid when ERR=1 in the Status register. Following a
 power on, reset, or completion of an Execute Drive Diagnostic
 command, this register contains a diagnostic code.


 PC-AT I/O port address: 1F2H
 This register specifies the number of sectors of data to be
 transferred during read/write sector commands. The value contained in
 the register is decremented every time a sector is transferred. A
 value of zero specifies 256 sectors. When executing the Initialize
 Drive Parameters or Format commands, this register defines the number
 of sectors per track.

 This register is used by the power mode commands to set timers.


 Sector Number register
 PC-AT I/O port address: 1F3H
 This register contains the starting sector number for any disc
 access. At the completion of a command, this register is updated to
 reflect the last sector transferred correctly, or the sector on which
 an error occurred. The sectors are numbered sequentially, starting
 with 1. With logical block addressing, this register contains bits 7
 through 0 of the logical block address (LBA).


